Hi. Im having problems understanding the segmentation mechanism in the x86 architecture.

So here is what i know:
There are 6 segment registers for example CS and SS.
The hold a 13 bit pointer, and indicator if the pointer is about LDT or GDT, and 2 bit requested privilege level. Now when i issue a jump to CS:EAX, this is what is happening(if the TI is set to GDT):
the 13 bit offset from CS is beeing taken and added to the value of GDTR(the register that holds a pointer to the base of Global descriptor table), so that a particular sement descriptor can be found. Then the 32 bit adress of the segment is taken from the segment descriptor and eax is added to it, and we get a linear adress(for now, before i learn paging i think of them as physical adresses).

But what i don't understand or rather couldn't find any info about is the LDT. From what i read on the internet they say that if TI is set in a segment register, the 13 bit offset now applies to LDT instead of GDT. But it is not quite true. The pointer in the segment register is actually an offset inside the GDT that , and it is an actual segmnet descriptor that holds the adress of LDT. But what is LDTR for then? And how does one know what offset to use within the LDT if the only one has been used to get to the LDT?

Also, another question. I asked about it on the SAX. I heard that a LDT is assigned per process, but that isnt quite true either. They are assigned only for some processes. How do i know which ones?

I have a few more questions but i think i will postpone them untill my current problems are resolved.

Quite simply, I think being concerned with old-style memory segmentation isn't worth your time (though I have no idea what you're trying to do).
Any recent processor (386-class or newer) is capable of 32-bit addressing, and the segment registers are largely ignored in modern code.

From what I see on wikipedia, the GDT and LDT were designed to function as a sort of poor man's MMU. Nowadays, that sort of functionality is handled in the memory controller.

http://wiki.osdev.org/Segmentation

But as Tari said, this stuff isn't used anymore, so why bother?

From what i've heard the processors cannot skip the segmentation process. The segmentation is allways there, and even though the segment registers are not present in the code, they are in the mashine code. Im intrested in this because im writing a small for fun OS with my friend and its quite important to understand how it all works.

x86 processors do indeed begin in Real Mode, but you would usually stay in Real Mode only during the run of the bootloader. If you use something like GRUB for the bootloader, then it already spits you into Protected(/Long?) mode; if you go this path, you don't really have to worry about Real Mode and segmented memory.

"machine code" is the same thing as assembly, just in a different form. Segmentation support is still part of modern CPUs, yes, but it isn't used. You set the GDT once and that's it.



Best site I've found for learning to write an OS is this one: http://wiki.osdev.org/Getting_Started