Earlier this year, I purchased a couple of FM18W08-SG chips, which are Ferroelectric RAM chips designed to function like a 32 KB SRAM chip, but without losing contents when left unpowered. I have recently installed one in my TI-85 and it has so far worked seamlessly as a drop-in substitute for the usual SRAM chip:

- Indistinguishable from an unmodified TI-85 in normal operation
- Passes the self-test
- Memory does clear upon next boot if checksum fails, such as after pulling a battery while busy graphing

The memory contents are indeed retained even if all batteries, including the backup coin cell, are pulled for an extended period of time. Admittedly, this is of limited use on the TI-85 on account of the backup batteries lasting upwards of 10 years, often still going strong after 25 years. This would be more notable of a mod on early TI-81 units which sold without the backup battery slot or on devices with more valuable data such as organizers and PDAs. I simply chose to do this on my TI-85 since I could easily access the SOP-28 SRAM chip and I did not mind sacrificing it if anything went wrong.

A couple of disadvantages come to mind:

- SRAM endurance is effectively infinite, but FRAM is rated for a countable number of program/erase cycles, 100 trillion in the case of the FM18W08-SG. I won't pretend to know how to calculate how quickly the TI-85 would eat through those cycles, but I will report back if any signs of degradation set in.

- There are certain crashes among TI calculators that require a hard memory clear, which is usually trivial to accomplish by pulling all batteries along with the backup coin cell. This no longer trivial with the non-volatile FRAM.

Now if only they made more compact SOP-28 sockets, then I would be on to making a sort of "TI-85 Plus".
Pi Time wrote:
SRAM endurance is effectively infinite, but FRAM is rated for a countable number of program/erase cycles, 100 trillion in the case of the FM18W08-SG. I won't pretend to know how to calculate how quickly the TI-85 would eat through those cycles, but I will report back if any signs of degradation set in.
It's worse than that! At least this chip (I don't know about FRAM in general) has destructive reads, so every read counts against the chip's endurance as well.

Page 4 of the FM18W08 datasheet (001-86207 Rev. *E):
Quote:
Internally, a F-RAM operates with a read and restore mechanism. Therefore, each read and write cycle involves a change of state. The memory architecture is based on an array of rows and columns. Each read or write access causes an endurance cycle for an entire row. In the FM18W08, a row is 64 bits wide. Every 8-byte boundary marks the beginning of a new row. Endurance can be optimized by ensuring frequently accessed data is located in different rows. Regardless, F-RAM offers substantially higher write endurance than other nonvolatile memories. The rated endurance limit of 1014 cycles will allow 150,000 accesses per second to the same row for over 20 years.


Assuming around 1 million RAM accesses per second while the calculator is running, you're down to a surprisingly short rated lifetime of only a few years (admittedly that's assuming continuous operation)!
  
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