I took a stab at reverse engineering some of the TI-80 hardware to shed more light on the circuitry and pins and produce a schematic and PCB layout that can be used as reference.

To recap, the hardware architecture contains four main devices: CPU ASIC, external ROM, external RAM, and LCD controller. These devices are wired together on a shared 8-bit bidirectional parallel bus and 15 bit address bus. There are separate chip select/chip enable control pins going to the individual ROM, RAM, LCD modules.

Full writeup and schematics are available in this repository: https://github.com/queueRAM/ti80_calculator

PCB layout and Schematics
Full schematic is included in this repository along with the notes used to markup the PCB photos. The schematic is broken into different sections grouping related components. It does not include all the individual test points, but includes the ones of interest. Full schematic is included in the repository as TI-80 schematic PDF or KiCad.


The PCB was reverse engineered using clean photos of the front and back PCB and marking up the traces in Inkscape and probing individual pins and vias. This was then captured in KiCad PCB layout in the repo. The repo contains both the KiCad PCB capture and the Inkscape SVG with layers for front, back, vias, labels, and notes.


Interesting findings:
(1) External ROM circuitry supports up to 16 address bits from the CPU, but A15 is tied high through J15 so only 32k are accessible. The ROM is likely only 32K.


(2) Pin 80 is unconnected, but strobes low for the duration of every external bus access (ROM, RAM, LCD). I named this pin `FRAME` in the schematic. Below is an example logic trace of it in action.


(3) Pin 52 is connected to a pull-up resistor R2 (1MΩ) so likely some sort of input. Tying this to GND doesn’t have obvious side effects. Need to investigate further.
(4) Pin 50 is wired out to a test pad, but not anything else. This is likely some test pin for debug or factory usage, but I have not observed anything interesting on it yet. Need to investigate further.


(5) J5 shorts one of the diodes used for reverse battery protection. This diode would like cause additional voltage drop and calculator becoming unusable due to the lower voltage powering the LCD.


(6) Calculator remains powered with only one battery installed, preserving the contents of SRAM. The slide switch in the battery compartment keeps /RST asserted while changing batteries. However, if manually de-asserted, the CPU, RAM, and ROM continue to run properly at 3V. The contrast of the LCD makes it unusable in this state. As an example, I was able to dump the external ROM at 3.3V.

(7) J17/J18 control which CPU pin is connected to ROM /CE (fitted J17 = pin 18, not-fitted J18 = pin 43). Pin 43 is closer to the other chip enable pins for LCD (41) and RAM (42). Not sure why there were options or why pin 18 was preferable.


I very much appreciate the documentation and assistance from the experts such as Zeroko who have looked at this before me. Adding most of my references here:

* ti80doc - TI-80 calculator HW/FW documentation
* ti80emu - TI-80 emulator
* DataMath | Texas Instruments TI-80 ViewScreen™
* MAME | TI-80 calculator CPU
* TI Planet | dumping TI-80
* Cemetech | Dumping TI-80 ROM directly
* Cemetech | TI-80 Hardware Revisions and ViewScreenification™
* Silicon Prawn | T6M53A die photos
* onidev | T6M53A die photos

2025-Aug-26 edit: updated to rev3 schematic and PCB renderings

I have been probing more on interesting findings (3) and (4) from initial post, I think pin 52 which is connected to R2 pull up resistor may be some sort of power/analog status pin or a voltage divider instead of an input as I originally hypothesized.

Measuring the analog values on pins 50 and 52 at the following points shows that Pin 50 is pretty much always low and pin 52 arrives at 3.3V after applying 5V power. It makes 1.45ms low pulse during power on reset and when /RST is de-asserted when the battery switch is slid in the middle position. When the `On`key is pressed, it goes low. I don't show it in the waveform below, but when turning off through button press, pin 52 goes back up 3.3V (under 5V VCC).


The 3.3V is just observed when using 5V VCC, but it is likely a ratio. When applying the following VCCs, I see this voltage on pin 25 when not powered on:
3.3V VCC → 2.18V
5V VCC → 3.3V
6V VCC → 4V

No change observed on these two pins when running through test mode, other than the above power observations when test mode completes and powers off.

I took the TI-80 schematic and went through the process of adding custom footprints and performing a PCB layout matching the original design. This isn't too necessary for reverse engineering, but I wanted to learn more about the process. I still need to correct the key foot prints so they align correctly and fixup the row/col routing because of this. Also, as part of this exercise, I realized I had the wrong pinout marked in the rev 1 schematic for the transistors and diodes in the graph link circuitry. This has now been corrected in the rev 2 schematic. Both rev2 schematic and PCB layout are pushed to the repo.


Having the PCB layout provides some neat features that the SVG I originally used to document the traces can't easily manage. Here is an example of highlighting the RAM /CS net. It takes a wild route going half-way down the PCB, between pins of three of the graph link components on the left side, and back up to the SRAM chip. I can't come up with a much better route given the constraints, but thought it was interesting.

I received a TI-80 ViewScreen and decided to look at the ViewScreen buffer board that was inside. I've added the schematic to the repo: https://github.com/queueRAM/ti80_calculator

This board connects to the main TI-80 PCB through the 16-pin ribbon cable. There are two 74HC244 octal tri-state buffers on this board which send buffered signals to the 26-pin external ViewScreen connector.


Interestingly, the order of the D0-D7 pins was not maintained from the ribbon to the DSub connector. On the ribbon cable, pins 1-8 map to D0-D7 in order. However, due to the 74HC244 buffer pinout used, D4-D7 are reversed on the DSub connector [D0..D3, D7..D4].
Code:


I was also curious to track down the ViewScreen connector. There is a "Suyin" manufacturer marking on it and 26 pins, but not much more info to go from. Suyin still makes connectors and has business in Taiwan and Europe, but no info on these type of connectors. After much more digging, I found that Suyin used to have presence in the USA and was able to track down a PDF of their catalog from early 2000s via Internet Archive of Suyin USA. Based on this, I think the connector on the PCB is the 127115FE series half pitch ultra thin D-Sub. The "E" indicates the edge mount, but I think the catalog has the wrong drawings listed. This seems to mate with the Suyin 127116 and 127120 series.


Kicad schematic is included in the repo along with PDF: