In the course of my efforts of documenting and emulating the Sitronix ST7789 LCD controller in the CE family calculators, I noticed that the internal clock rate (nominally 10 MHz) wasn't totally consistent between my different calculators.
This variance in clock rate is important to know when tuning timing parameters for VSYNC interface mode, because if a VSYNC signal (from the Primecell PL111 LCD controller) comes in before the Sitronix LCD controller is done scanning a frame, that signal is dropped and the refresh rate is halved. I noticed this discrepancy when developing TI-Boy CE against my multiple calculators. Ideally the timing parameters should target a frequency lower than the frequency of any known calculator's LCD controller.
Long story short, I've just developed a test program that allows visually tuning the refresh rate to as close to 60 Hz as possible, and prints the approximate clock rate based on the configured timings on exit. I'd like to collect information on as many calculators as possible to determine the range of clock rates expected in the wild. So far, signs point to this not being related to the revision, but I recommend sharing that for statistical purposes.
I'll start by sharing mine (model and datecode/revision):
TI-84+CE (L-0115): 10,010,880 Hz
TI-84+CE (L-0716C): 10,051,080 Hz
TI-83PCE Python (L-0419M): 9,887,640 Hz
My current idea of a "target clock rate" for VSYNC interface timing parameters is 9.8 MHz, but if anyone finds a clock rate slower than that, it may need to change.
This variance in clock rate is important to know when tuning timing parameters for VSYNC interface mode, because if a VSYNC signal (from the Primecell PL111 LCD controller) comes in before the Sitronix LCD controller is done scanning a frame, that signal is dropped and the refresh rate is halved. I noticed this discrepancy when developing TI-Boy CE against my multiple calculators. Ideally the timing parameters should target a frequency lower than the frequency of any known calculator's LCD controller.
Long story short, I've just developed a test program that allows visually tuning the refresh rate to as close to 60 Hz as possible, and prints the approximate clock rate based on the configured timings on exit. I'd like to collect information on as many calculators as possible to determine the range of clock rates expected in the wild. So far, signs point to this not being related to the revision, but I recommend sharing that for statistical purposes.
I'll start by sharing mine (model and datecode/revision):
TI-84+CE (L-0115): 10,010,880 Hz
TI-84+CE (L-0716C): 10,051,080 Hz
TI-83PCE Python (L-0419M): 9,887,640 Hz
My current idea of a "target clock rate" for VSYNC interface timing parameters is 9.8 MHz, but if anyone finds a clock rate slower than that, it may need to change.
